Пакет: yosys-abc (0.33-6)

[ Източник: yosys  ]

Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

Други пакети, свързани с yosys-abc

• dep: libbz2-1.0

  high-quality block-sorting file compressor library - runtime

• dep: libc6 (>= 2.38)

  GNU C Library: Shared libraries
  също и виртуален пакет, предлаган от libc6-udeb

• dep: libgcc-s1 (>= 3.3.1)

  GCC support library

• dep: libreadline8t64 (>= 6.0)

  GNU readline and history libraries, run-time libraries

• dep: libstdc++6 (>= 13.1)

  GNU Standard C++ Library v3

• dep: zlib1g (>= 1:1.1.4)

  compression library - runtime

Изтегляне на yosys-abc

Изтегляне за всички налични архитектури

Архитектура	Големина на пакета	Големина след инсталиране	Файлове
arm64	4 781,1 кБ	14 568,0 кБ	[списък на файловете]