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Package: yosys-abc (0.33-6 and others)

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Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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Download yosys-abc

Download for all available architectures
Architecture Version Package Size Installed Size Files
alpha (unofficial port) 0.33-5+b2 5,056.0 kB17,179.0 kB [list of files]
amd64 0.33-6 5,351.1 kB14,895.0 kB [list of files]
arm64 0.33-6 4,781.1 kB14,568.0 kB [list of files]
armel 0.33-6 4,564.3 kB13,861.0 kB [list of files]
armhf 0.33-6 4,742.0 kB10,597.0 kB [list of files]
i386 0.33-6 5,569.6 kB16,568.0 kB [list of files]
m68k (unofficial port) 0.33-5+b2 5,145.3 kB15,917.0 kB [list of files]
mips64el 0.33-6 4,954.3 kB18,524.0 kB [list of files]
ppc64el 0.33-6 5,527.9 kB18,472.0 kB [list of files]
riscv64 0.33-6 5,406.1 kB13,031.0 kB [list of files]
sh4 (unofficial port) 0.33-5+b2 5,847.3 kB13,853.0 kB [list of files]
x32 (unofficial port) 0.33-6 5,347.4 kB14,605.0 kB [list of files]