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软件包:yosys-abc(0.33-5 以及其他的)

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Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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下载 yosys-abc

下载可用于所有硬件架构的
硬件架构 版本 软件包大小 安装后大小 文件
alpha (非官方移植版) 0.33-5+b2 5,056.0 kB17,179.0 kB [文件列表]
amd64 0.33-5+b2 5,315.4 kB14,688.0 kB [文件列表]
arm64 0.33-5+b2 4,750.9 kB14,504.0 kB [文件列表]
armel 0.33-5+b2 4,564.0 kB13,830.0 kB [文件列表]
armhf 0.33-5+b2 4,726.5 kB10,542.0 kB [文件列表]
i386 0.33-5+b2 5,544.8 kB16,397.0 kB [文件列表]
m68k (非官方移植版) 0.33-5+b2 5,145.3 kB15,917.0 kB [文件列表]
mips64el 0.33-5+b2 4,868.0 kB18,271.0 kB [文件列表]
ppc64el 0.33-5+b2 5,526.4 kB18,473.0 kB [文件列表]
riscv64 0.33-5+b3 5,446.0 kB13,108.0 kB [文件列表]
sh4 (非官方移植版) 0.33-5+b2 5,847.3 kB13,853.0 kB [文件列表]
x32 (非官方移植版) 0.33-5+b2 5,312.8 kB14,410.0 kB [文件列表]