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Pakket: yosys-abc (0.51-1 en anderen)

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Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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Pakket downloaden voor alle beschikbare platforms
Platform Versie Pakketgrootte Geïnstalleerde grootte Bestanden
alpha (unofficial port) 0.51-1 4.261,8 kB13.364,0 kB [overzicht]
amd64 0.51-1 4.487,5 kB11.895,0 kB [overzicht]
arm64 0.51-1 3.965,0 kB11.139,0 kB [overzicht]
loong64 (unofficial port) 0.51-1 4.225,9 kB12.035,0 kB [overzicht]
m68k (unofficial port) 0.51-1 4.227,4 kB12.297,0 kB [overzicht]
mips64el 0.51-1 4.101,3 kB14.001,0 kB [overzicht]
ppc64el 0.51-1 4.550,2 kB14.211,0 kB [overzicht]
riscv64 0.51-1 4.456,4 kB9.959,0 kB [overzicht]
sh4 (unofficial port) 0.33-6 5.831,5 kB13.788,0 kB [overzicht]
x32 (unofficial port) 0.33-6 5.347,4 kB14.605,0 kB [overzicht]