Package: yosys-abc (0.51-1)

[ Source: yosys  ]

Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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Architecture	Package Size	Installed Size	Files
amd64	4,487.5 kB	11,895.0 kB	[list of files]
arm64	3,965.0 kB	11,139.0 kB	[list of files]
mips64el	4,101.3 kB	14,001.0 kB	[list of files]
ppc64el	4,550.2 kB	14,211.0 kB	[list of files]
riscv64	4,456.4 kB	9,959.0 kB	[list of files]