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Package: yosys-abc (0.51-1 and others)

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Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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Download yosys-abc

Download for all available architectures
Architecture Version Package Size Installed Size Files
alpha (unofficial port) 0.51-1 4,261.8 kB13,364.0 kB [list of files]
amd64 0.51-1 4,487.5 kB11,895.0 kB [list of files]
arm64 0.51-1 3,965.0 kB11,139.0 kB [list of files]
armel 0.33-6 4,564.3 kB13,861.0 kB [list of files]
armhf 0.33-6 4,742.0 kB10,597.0 kB [list of files]
i386 0.33-6 5,569.6 kB16,568.0 kB [list of files]
m68k (unofficial port) 0.51-1 4,227.4 kB12,297.0 kB [list of files]
mips64el 0.51-1 4,101.3 kB14,001.0 kB [list of files]
ppc64el 0.51-1 4,550.2 kB14,211.0 kB [list of files]
riscv64 0.51-1 4,456.4 kB9,959.0 kB [list of files]
sh4 (unofficial port) 0.33-6 5,831.5 kB13,788.0 kB [list of files]
x32 (unofficial port) 0.33-6 5,347.4 kB14,605.0 kB [list of files]