Balík: verilator (5.024-1 a iné)

[ Zdroj: verilator  ]

fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Značky: Pole: Elektronika, Implementované v: C++, implemented-in::perl, interface::commandline, Role: Program, Purpose: Simulating

Ostatné balíky súvisiace s balíkom verilator

• dep: libjs-sphinxdoc (>= 7.4)

  podpora JavaScriptu v dokumentácii Sphinx

• dep: perl

  Practical Extraction and Report Language od Larryho Walla

• dep: python3

  interactive high-level object-oriented language (default python3 version)

• dep: sphinx-rtd-theme-common (>= 2.0.0+dfsg)

  téma vzhľadu pre sphinx z readthedocs.org - spoločné súbory

• rec: libsystemc-dev

  Development files for SystemC library

• sug: gtkwave

  zobrazovač vĺn súborov VCD (Value Change Dump)

Stiahnuť verilator

Stiahnuť pre všetky dostupné architektúry

Architektúra	Verzia	Veľkosť balíka	Nainštalovaná veľkosť	Súbory
i386	5.024-1+b2	1,405.4 kB	4,191.0 kB	[zoznam súborov]