Package: yosys-abc (0.52-1)

[ Source: yosys  ]

Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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Architecture	Package Size	Installed Size	Files
amd64	4,828.4 kB	12,925.0 kB	[list of files]
arm64	4,271.4 kB	12,054.0 kB	[list of files]
armel	4,085.1 kB	11,854.0 kB	[list of files]
armhf	4,253.4 kB	8,910.0 kB	[list of files]
i386	4,902.5 kB	13,881.0 kB	[list of files]
mips64el	4,413.2 kB	15,073.0 kB	[list of files]
ppc64el	4,906.4 kB	15,382.0 kB	[list of files]
riscv64	4,798.1 kB	10,774.0 kB	[list of files]