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Pacote: yosys-abc (0.51-1)

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Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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Download de yosys-abc

Baixe para todas as arquiteturas disponíveis
Arquitetura Tamanho do pacote Tamanho instalado Arquivos
amd64 4,487.5 kB11,895.0 kB [lista de arquivos]
arm64 3,965.0 kB11,139.0 kB [lista de arquivos]
mips64el 4,101.3 kB14,001.0 kB [lista de arquivos]
ppc64el 4,550.2 kB14,211.0 kB [lista de arquivos]
riscv64 4,456.4 kB9,959.0 kB [lista de arquivos]