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套件:yosys-abc(0.51-1)

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Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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下載 yosys-abc

下載可用於所有硬體架構的
硬體架構 套件大小 安裝後大小 檔案
amd64 4,487。5 kB11,895。0 kB [檔案列表]
arm64 3,965。0 kB11,139。0 kB [檔案列表]
mips64el 4,101。3 kB14,001。0 kB [檔案列表]
ppc64el 4,550。2 kB14,211。0 kB [檔案列表]
riscv64 4,456。4 kB9,959。0 kB [檔案列表]