软件包：yosys（0.6-7 以及其他的） [debports]
Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.
其他与 yosys 有关的软件包
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- dep: berkeley-abc (>= 1.01)
- ABC - A System for Sequential Synthesis and Verification
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- dep: libc6 (>= 2.11)
- GNU C 语言运行库：共享库
同时作为一个虚包由这些包填实： libc6-udeb
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- dep: libffi6 (>= 3.0.4)
- 软件包暂时不可用
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- dep: libgcc1 (>= 1:3.0)
- 软件包暂时不可用
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- dep: libreadline7 (>= 6.0)
- 软件包暂时不可用
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- dep: libstdc++6 (>= 5.2)
- GNU 标准 C++ 库，第3版
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- dep: libtcl8.6 (>= 8.6.0)
- Tcl (the Tool Command Language) v8.6 - run-time library files
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- dep: python3
- interactive high-level object-oriented language (default python3 version)
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- dep: xdot
- interactive viewer for Graphviz dot files