Paket: verilator (5.012-1 ve diğerleri) [debports]

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fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

verilator ile İlgili Diğer Paketler

• dep: libc6.1 (>= 2.37)

  GNU C Library: Shared libraries
  ayrıca şunun tarafından sağlanan bir sanal paket libc6.1-udeb

• dep: libjs-sphinxdoc (>= 5.2)

  JavaScript support for Sphinx documentation

• dep: perl

  Larry Wall's Practical Extraction and Report Language

• dep: python3

  interactive high-level object-oriented language (default python3 version)

• dep: sphinx-rtd-theme-common (>= 1.2.2+dfsg)

  sphinx theme from readthedocs.org (common files)

• rec: libsystemc-dev

  Development files for SystemC library

• sug: gtkwave

  VCD (Value Change Dump) file waveform viewer

verilator indir

Tüm mevcut mimariler için indir

Mimari	Sürüm	Paket Boyutu	Kurulu Boyut	Dosyalar
ia64 (resmi olmayan port)	5.012-1+b1	8.612,6 kB	75.801,0 kB	[dosya listesi]