Paket: yosys (0.8-1)

[ Kaynak: yosys  ]

Framework for Verilog RTL synthesis

This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.

yosys ile İlgili Diğer Paketler

• dep: berkeley-abc (>= 1.01+20161002hgeb6eca6+dfsg)

  ABC - A System for Sequential Synthesis and Verification

• dep: libc6 (>= 2.27)

  GNU C Library: Shared libraries
  ayrıca şunun tarafından sağlanan bir sanal paket libc6-udeb

• dep: libffi6 (>= 3.2)

  Foreign Function Interface library runtime

• dep: libgcc1 (>= 1:3.0)

  GCC support library

• dep: libreadline7 (>= 6.0)

  GNU readline and history libraries, run-time libraries

• dep: libstdc++6 (>= 5.2)

  GNU Standard C++ Library v3

• dep: libtcl8.6 (>= 8.6.0)

  Tcl (the Tool Command Language) v8.6 - run-time library files

• dep: python3

  interactive high-level object-oriented language (default python3 version)

• dep: xdot

  interactive viewer for Graphviz dot files

yosys indir

Tüm mevcut mimariler için indir

Mimari	Paket Boyutu	Kurulu Boyut	Dosyalar
arm64	1.618,5 kB	6.592,0 kB	[dosya listesi]