软件包：yosys（0.8-1）

[ 源代码： yosys  ]

Framework for Verilog RTL synthesis

This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.

其他与 yosys 有关的软件包

• dep: berkeley-abc (>= 1.01+20161002hgeb6eca6+dfsg)

  ABC - A System for Sequential Synthesis and Verification

• dep: libc6 (>= 2.27)

  GNU C 语言运行库：共享库
  同时作为一个虚包由这些包填实： libc6-udeb

• dep: libffi6 (>= 3.2)

  外部函数接口库运行环境

• dep: libgcc1 (>= 1:3.0)

  GCC 支持库

• dep: libreadline7 (>= 6.0)

  GNU readline 与 history 库，运行时

• dep: libstdc++6 (>= 5.2)

  GNU 标准 C++ 库，第3版

• dep: libtcl8.6 (>= 8.6.0)

  Tcl (the Tool Command Language) v8.6 - run-time library files

• dep: python3

  交互式高级面向对象语言（默认 python3 版本）

• dep: xdot

  interactive viewer for Graphviz dot files

下载 yosys

下载可用于所有硬件架构的

硬件架构	软件包大小	安装后大小	文件
arm64	1,618.5 kB	6,592.0 kB	[文件列表]