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[ Source: yosys  ]

Package: yosys (0.52-1 and others)

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infrastruttura per la sintesi di RTL Verilog

Questa è un'infrastruttura per la sintesi di RTL Verilog. Attualmente ha una gestione ampia di Verilog-2005 e fornisce un insieme di base di algoritmi di sintesi per svariati domini d'applicazione.

Yosys può essere adattato per eseguire qualsiasi lavoro di sintesi combinando i passaggi esistenti (algoritmi) usando script di sintesi e aggiungendo i passaggi aggiuntivi necessari estendendo la base di codice C++ di Yosys.

Other Packages Related to yosys

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Download yosys

Download for all available architectures
Architecture Version Package Size Installed Size Files
alpha (unofficial port) 0.52-1 5,489.4 kB28,313.0 kB [list of files]
amd64 0.52-1 6,079.7 kB25,753.0 kB [list of files]
arm64 0.52-1 5,232.3 kB24,305.0 kB [list of files]
armel 0.52-1 5,218.2 kB24,560.0 kB [list of files]
armhf 0.52-1 5,446.9 kB19,952.0 kB [list of files]
hppa (unofficial port) 0.12-1 3,017.8 kB16,641.0 kB [list of files]
i386 0.52-1 6,274.3 kB26,722.0 kB [list of files]
ia64 (unofficial port) 0.23-6 3,401.3 kB22,772.0 kB [list of files]
loong64 (unofficial port) 0.52-1 5,405.9 kB24,497.0 kB [list of files]
m68k (unofficial port) 0.52-1 5,410.5 kB24,360.0 kB [list of files]
mips64el 0.52-1 4,808.0 kB27,018.0 kB [list of files]
ppc64 (unofficial port) 0.9-2+b1 2,026.7 kB9,448.0 kB [list of files]
ppc64el 0.52-1 5,700.9 kB27,505.0 kB [list of files]
riscv64 0.52-1 5,895.2 kB22,201.0 kB [list of files]
sh4 (unofficial port) 0.33-6 3,737.9 kB13,130.0 kB [list of files]
sparc64 (unofficial port) 0.6-7+b1 1,267.7 kB5,329.0 kB [list of files]
x32 (unofficial port) 0.52-1 5,902.7 kB24,639.0 kB [list of files]