Package: yosys (0.33-5 and others)

[ Source: yosys  ]

Ramme for Verilog RTL-syntese

Dette er en ramme for Verilog RTL-syntese. Det har i øjeblikket omfattende Verilog-2005-understøttelse og tilbyder et grundlæggende sæt af syntesealgoritmer for diverse programdomæner.

Yosys kan tilpasse til at udføre alle syntesejob ved at kombinere de eksisterende gennemløb (algoritmer) via synteseskripter og tilføje yderligere gennemløb efter behov ved at udvide yosys C++-kodebasen.

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  dep: berkeley-abc (>= 1.01+20211229git48498af+dfsg) [hppa]

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Download yosys

Download for all available architectures

Architecture	Version	Package Size	Installed Size	Files
alpha (unofficial port)	0.33-5+b2	2,846.1 kB	14,892.0 kB	[list of files]
amd64	0.33-5+b2	2,951.5 kB	12,434.0 kB	[list of files]
arm64	0.33-5+b2	2,602.7 kB	12,366.0 kB	[list of files]
armel	0.33-5+b2	2,660.2 kB	12,081.0 kB	[list of files]
armhf	0.33-5+b2	2,745.0 kB	10,189.0 kB	[list of files]
hppa (unofficial port)	0.12-1	3,017.8 kB	16,641.0 kB	[list of files]
i386	0.33-5+b2	2,976.8 kB	12,665.0 kB	[list of files]
ia64 (unofficial port)	0.23-6	3,401.3 kB	22,772.0 kB	[list of files]
m68k (unofficial port)	0.33-5+b2	2,925.9 kB	12,593.0 kB	[list of files]
mips64el	0.33-5+b2	2,493.5 kB	14,391.0 kB	[list of files]
ppc64 (unofficial port)	0.9-2+b1	2,026.7 kB	9,448.0 kB	[list of files]
ppc64el	0.33-5+b2	2,713.0 kB	13,262.0 kB	[list of files]
riscv64	0.33-5+b3	2,921.5 kB	11,706.0 kB	[list of files]
sh4 (unofficial port)	0.33-5+b2	3,671.5 kB	13,131.0 kB	[list of files]
sparc64 (unofficial port)	0.6-7+b1	1,267.7 kB	5,329.0 kB	[list of files]
x32 (unofficial port)	0.33-5+b2	2,952.8 kB	11,937.0 kB	[list of files]