Paketti: verilator (4.038-1)

[ Source: verilator  ]

fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Tagit: Field: Elektroniikka, Implemented in: C++, implemented-in::perl, interface::commandline, Role: Program, Purpose: Simulating

Muut pakettiin verilator liittyvät paketit

• dep: libc6 (>= 2.29)

  GNU-C-kirjasto: jaetut kirjastot
  myös näennäispaketti, jonka toteuttaa libc6-udeb

• rec: libsystemc-dev

  Development files for SystemC library

• sug: gtkwave

  VCD (Value Change Dump) file waveform viewer

Imuroi verilator

Imurointi kaikille saataville arkkitehtuureille

Arkkitehtuuri	Paketin koko	Koko asennettuna	Tiedostot
amd64	4,617.4 kt	20,379.0 kt	[tiedostoluettelo]