Пакет: opensta (0~20191111gitc018cb2+dfsg-1) [debports]

[ Източник:  ]

Gate-level Static Timing Analyzer

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

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• dep: libgcc1 (>= 1:3.0)

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• dep: libtcl8.6 (>= 8.6.0)

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• dep: zlib1g (>= 1:1.1.4)

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