套件：opensta（0~20191111gitc018cb2+dfsg-1） [debports]
Gate-level Static Timing Analyzer
After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.
It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.
其他與 opensta 有關的套件
|
|
|
|
-
- dep: libc6 (>= 2.29)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6-udeb
-
- dep: libgcc1 (>= 1:3.0)
- 套件暫時不可用
-
- dep: libreadline8 (>= 6.0)
- GNU readline 與 history 函式庫，執行時期函式庫
-
- dep: libstdc++6 (>= 6)
- GNU Standard C++ Library v3
-
- dep: libtcl8.6 (>= 8.6.0)
- Tcl (the Tool Command Language) v8.6 - run-time library files
-
- dep: zlib1g (>= 1:1.1.4)
- 壓縮函式庫 - 跑程式時用(runtime)