套件：covered（0.7.10-5）

[ 原始碼： covered  ]

Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

標籤: 領域: 電子學, 實做語言: C, 使用者介面: interface::commandline, interface::graphical, X 視窗系統, 角色: 程式, Interface Toolkit: uitoolkit::tk, use::viewing, X 視窗系統: 應用程式

其他與 covered 有關的套件

• dep: libc6 (>= 2.34)

  GNU C 函式庫：共用函式庫
  同時作為一個虛擬套件由這些套件填實： libc6-udeb

• dep: libtcl8.6 (>= 8.6.0)

  Tcl (the Tool Command Language) v8.6 - run-time library files

• dep: libtk8.6 (>= 8.6.0)

  Tk toolkit for Tcl and X11 v8.6 - run-time files

• dep: tklib

  standard Tk Library

• dep: zlib1g (>= 1:1.1.4)

  壓縮函式庫 - 跑程式時用(runtime)

• rec: iverilog

  Icarus verilog compiler

  或者 verilog

  本虛擬套件由這些套件填實： iverilog

  或者 gplcver (>= 2.12a-1.1)

  Verilog simulator

下載 covered

下載可用於所有硬體架構的

硬體架構	套件大小	安裝後大小	檔案
s390x	519。4 kB	2，565。0 kB	[檔案列表]