Package: covered (0.7.10-5)
Links for covered
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Download Source Package covered:
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External Resources:
- Homepage [covered.sourceforge.net]
Similar packages:
Verilog code coverage analysis tool
Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.
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Download covered
Architecture | Package Size | Installed Size | Files |
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s390x | 519.4 kB | 2,565.0 kB | [list of files] |