[ 原始碼： verilator ]
套件：verilator（4.010-1）
fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
其他與 verilator 有關的套件
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- dep: libc6 (>= 2.28)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6-udeb
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- dep: libgcc1 (>= 1:4.2)
- GCC 支援函式庫
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- dep: libstdc++6 (>= 5.2)
- GNU Standard C++ Library v3
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- rec: libsystemc-dev
- Development files for SystemC library
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- sug: gtkwave
- VCD (Value Change Dump) file waveform viewer