[ 源代码： iverilog ]
软件包：iverilog（10.2-1.1）
Icarus verilog compiler
Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.
The compiler can target either simulation, or netlist (EDIF).
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