[ 源代码: iverilog ]
软件包:iverilog(11.0-1)
Icarus verilog compiler
Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.
The compiler can target either simulation, or netlist (EDIF).
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下载 iverilog
硬件架构 | 软件包大小 | 安装后大小 | 文件 |
---|---|---|---|
amd64 | 1,962.2 kB | 6,872.0 kB | [文件列表] |
arm64 | 1,754.2 kB | 6,637.0 kB | [文件列表] |
armel | 1,673.8 kB | 5,847.0 kB | [文件列表] |
armhf | 1,730.0 kB | 4,616.0 kB | [文件列表] |
i386 | 2,060.6 kB | 6,933.0 kB | [文件列表] |
mips64el | 1,646.7 kB | 8,235.0 kB | [文件列表] |
mipsel | 1,669.5 kB | 7,470.0 kB | [文件列表] |
ppc64el | 1,948.8 kB | 8,842.0 kB | [文件列表] |
s390x | 1,777.3 kB | 7,085.0 kB | [文件列表] |