[ 源代码: covered ]
软件包:covered(0.7.10-3 以及其他的)
Verilog code coverage analysis tool
Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.
其他与 covered 有关的软件包
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- dep: libc6 (>= 2.11) [armhf, i386]
- GNU C 语言运行库:共享库
同时作为一个虚包由这些包填实: libc6-udeb
- dep: libc6 (>= 2.14) [amd64]
- dep: libc6 (>= 2.17) [arm64]
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- dep: libtcl8.6 (>= 8.6.0)
- Tcl (the Tool Command Language) v8.6 - run-time library files
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- dep: libtk8.6 (>= 8.6.0)
- 用于 Tcl 和 X11 的 Tk 工具箱 8.6 版 - 运行时文件
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- dep: tklib
- standard Tk Library
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- dep: zlib1g (>= 1:1.1.4)
- 压缩库 - 运行时