Пакет: covered-doc (0.7.10-5)

[ Источник: covered  ]

Verilog code coverage analysis tool - documentation

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

This package contains the documentation.

Теги: Роль: Документация

Загрузка covered-doc

Загрузить для всех доступных архитектур

Архитектура	Размер пакета	В установленном виде	Файлы
all	1 650,5 Кб	2 438,0 Кб	[список файлов]