[ sid ]
[ experimental ]
Pakket: yosys-abc (0.33-6) [debports]
Verwijzigingen voor yosys-abc
Debian bronnen:
Het bronpakket downloaden:
Niet gevondenBeheerders:
Externe bronnen:
- Homepage [github.com]
Vergelijkbare pakketten:
Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.
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