Paketti: arachne-pnr (0.1+20190728gitc40fb22-3)

[ Source: arachne-pnr  ]

Place and route tool for iCE40 family FPGAs

Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device.

Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development.

The authors of arachne-pnr have now prepared its successor 'nextpnr'.

Muut pakettiin arachne-pnr liittyvät paketit

• dep: arachne-pnr-chipdb

  Chip db files for arachne-pnr

• dep: fpga-icestorm

  Tools to handle the bitstream format of Lattice iCE40 FPGAs

• dep: libc6 (>= 2.34)

  GNU-C-kirjasto: jaetut kirjastot
  myös näennäispaketti, jonka toteuttaa libc6-udeb

• dep: libgcc-s1 (>= 3.0)

  GCC:n apukirjasto

• dep: libstdc++6 (>= 11)

  GNU standardi C++ -kirjasto, versio 3

• sug: nextpnr

  Paketti ei saatavilla

• sug: yosys

  Framework for Verilog RTL synthesis

Imuroi arachne-pnr

Imurointi kaikille saataville arkkitehtuureille

Arkkitehtuuri	Paketin koko	Koko asennettuna	Tiedostot
mips64el	186.1 kt	814.0 kt	[tiedostoluettelo]