Paketti: arachne-pnr-chipdb (0.1+20190728gitc40fb22-3)

[ Source: arachne-pnr  ]

Chip db files for arachne-pnr

Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device.

This package contains the binary versions of the chipdb files needed by arachne-pnr

Imuroi arachne-pnr-chipdb

Imurointi kaikille saataville arkkitehtuureille

Arkkitehtuuri	Paketin koko	Koko asennettuna	Tiedostot
all	6,313.5 kt	28,525.0 kt	[tiedostoluettelo]