Package: verilator (5.024-1 and others)

[ Source: verilator  ]

fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Tags: Field: Electronics, Implemented in: C++, implemented-in::perl, interface::commandline, Role: Program, Purpose: Simulating

Other Packages Related to verilator

• dep: libjs-sphinxdoc (>= 7.4)

  JavaScript support for Sphinx documentation

• dep: perl

  Larry Wall's Practical Extraction and Report Language

• dep: python3

  interactive high-level object-oriented language (default python3 version)

• dep: sphinx-rtd-theme-common (>= 2.0.0+dfsg)

  sphinx theme from readthedocs.org (common files)

• sug: gtkwave

  VCD (Value Change Dump) file waveform viewer

Download verilator

Download for all available architectures

Architecture	Version	Package Size	Installed Size	Files
armhf	5.024-1+b2	1,405.3 kB	4,191.0 kB	[list of files]