Paket: verilator (5.024-1 und andere)

[ Quellcode: verilator  ]

fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Markierungen: Feld: Elektronik, Implementiert in: C++, implemented-in::perl, interface::commandline, Rolle: Programm, Zweck: Simulierung

Andere Pakete mit Bezug zu verilator

• dep: libjs-sphinxdoc (>= 7.4)

  JavaScript-Unterstützung für Sphinx-Dokumentation

• dep: perl

  Larry Wall's Practical Extraction und Report Language

• dep: python3

  interactive high-level object-oriented language (default python3 version)

• dep: sphinx-rtd-theme-common (>= 2.0.0+dfsg)

  sphinx theme from readthedocs.org (common files)

• sug: gtkwave

  Signalform-Betrachter für VCD-Dateien (Value Change Dump)

verilator herunterladen

Download für alle verfügbaren Architekturen

Architektur	Version	Paketgröße	Größe (installiert)	Dateien
armhf	5.024-1+b2	1.405,3 kB	4.191,0 kB	[Liste der Dateien]