Пакет: covered (0.7.10-4) [debports]

[ Източник:  ]

Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Други пакети, свързани с covered

• dep: libc6.1 (>= 2.36)

  GNU C Library: Shared libraries
  също и виртуален пакет, предлаган от libc6.1-udeb

• dep: libtcl8.6 (>= 8.6.0)

  Tcl (the Tool Command Language) v8.6 - run-time library files

• dep: libtk8.6 (>= 8.6.0)

  Tk toolkit for Tcl and X11 v8.6 - run-time files

• dep: tklib

  standard Tk Library

• dep: zlib1g (>= 1:1.1.4)

  compression library - runtime

• rec: iverilog

  Icarus verilog compiler

  или verilog

  виртуален пакет, предлаган от iverilog

  или gplcver (>= 2.12a-1.1)

  Verilog simulator

Изтегляне на covered

Изтегляне за всички налични архитектури

Архитектура	Големина на пакета	Големина след инсталиране	Файлове
ia64 (неофициална архитектура)	591,7 кБ	4 022,0 кБ	[списък на файловете]