Пакет: iverilog (10.2-1.1)

[ Източник: iverilog  ]

Icarus verilog compiler

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

Етикети: Field: Електроника, Implemented in: C++, User Interface: interface::commandline, role::program

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Архитектура	Големина на пакета	Големина след инсталиране	Файлове
amd64	1 798,2 кБ	6 267,0 кБ	[списък на файловете]