Пакет: verilator (5.006-3)

[ Източник: verilator  ]

fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Етикети: Field: Електроника, Implemented in: C++, implemented-in::perl, interface::commandline, Role: Program, Purpose: Simulating

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• dep: perl

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• dep: python3

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• dep: sphinx-rtd-theme-common (>= 1.2.0+dfsg)

  sphinx theme from readthedocs.org (common files)

• rec: libsystemc-dev

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• sug: gtkwave

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Архитектура	Големина на пакета	Големина след инсталиране	Файлове
mips64el	5 536,9 кБ	39 448,0 кБ	[списък на файловете]