原始碼套件:covered(0.7.10-5)
本原始碼套件構建了以下這些二進位制包:
- covered
- Verilog code coverage analysis tool
- covered-doc
- Verilog code coverage analysis tool - documentation
其他與 covered 有關的套件
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- adep: debhelper-compat (= 13)
- 套件暫時不可用
-
- adep: flex
- fast lexical analyzer generator
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- adep: bison
- YACC-compatible parser generator
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- adep: gperf
- Perfect hash function generator
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- adep: tcl-dev
- Tool Command Language (default version) - development files
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- adep: tk-dev
- Toolkit for Tcl and X11 (default version) - development files
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- adep: libxft2-dev
- 本虛擬套件由這些套件填實: libxft-dev
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- adep: gplcver (>= 2.12a-1.1)
- Verilog simulator
Download covered
檔案 | 大小(單位:kB) | MD5 校驗碼 |
---|---|---|
covered_0.7.10-5.dsc | 1。8 kB | 460d515f060447bafa7116ee1dadc9b4 |
covered_0.7.10.orig.tar.gz | 3,035。4 kB | 7f79e93471546810b166e9104236bda2 |
covered_0.7.10-5.debian.tar.xz | 6。3 kB | 7226f6b027e23f8cf086af1db4ea734e |
- Debian 套件原始碼倉庫(VCS:Git)
- https://salsa.debian.org/electronics-team/covered.git
- Debian 套件原始碼倉庫(可線上瀏覽)
- https://salsa.debian.org/electronics-team/covered