原始碼套件：covered（0.7.10-3.1）
本原始碼套件構建了以下這些二進位制包：
- covered
- Verilog code coverage analysis tool
- covered-doc
- Verilog code coverage analysis tool - documentation
其他與 covered 有關的套件
|
|
-
- adep: debhelper (>= 9)
- helper programs for debian/rules
-
- adep: autotools-dev
- Update infrastructure for config.{guess,sub} files
-
- adep: flex
- fast lexical analyzer generator
-
- adep: bison
- YACC-compatible parser generator
-
- adep: gperf
- Perfect hash function generator
-
- adep: tcl-dev
- Tool Command Language (default version) - development files
-
- adep: tk-dev
- Toolkit for Tcl and X11 (default version) - development files
-
- adep: libxft2-dev
- 本虛擬套件由這些套件填實： libxft-dev
-
- adep: gplcver (>= 2.12a-1.1)
- Verilog simulator
Download covered
| 檔案 | 大小（單位：kB） | MD5 校驗碼 |
|---|---|---|
| covered_0.7.10-3.1.dsc | 2。1 kB | 6f70f6b417c7c824ba92b6edc5ff36aa |
| covered_0.7.10.orig.tar.gz | 3，035。4 kB | 7f79e93471546810b166e9104236bda2 |
| covered_0.7.10-3.1.debian.tar.xz | 4。9 kB | c1ed34ff00c75a465d4250d53de8be3b |
- Debian 套件原始碼倉庫（VCS：Git）
- git://anonscm.debian.org/pkg-electronics/covered.git
- Debian 套件原始碼倉庫（可線上瀏覽）
- http://anonscm.debian.org/gitweb/?p=pkg-electronics/covered.git