[ 原始碼： opensta ]
套件：opensta-dev（0~20191111gitc018cb2+dfsg-1.1）
opensta-dev 的相關連結
Debian 的資源：
下載原始碼套件 opensta：
- [opensta_0~20191111gitc018cb2+dfsg-1.1.dsc]
- [opensta_0~20191111gitc018cb2+dfsg.orig.tar.xz]
- [opensta_0~20191111gitc018cb2+dfsg-1.1.debian.tar.xz]
維護小組：
外部的資源：
- 主頁 [github.com]
相似套件：
Gate-level Static Timing Analyzer - development files
After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.
It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.
This package contains the header files and some libraries for development.