[ 原始碼： yosys ]
套件：yosys-doc（0.33-5）
yosys-doc 的相關連結
Debian 的資源：
下載原始碼套件 yosys：
- [yosys_0.33-6.dsc]
- [yosys_0.33.orig-abc.tar.gz]
- [yosys_0.33.orig.tar.gz]
- [yosys_0.33-6.debian.tar.xz]
維護小組：
- Debian Science Maintainers (QA 頁面, 郵件存檔)
- Ruben Undheim (QA 頁面)
- Sebastian Kuzminsky (QA 頁面)
- Daniel Gröber (QA 頁面)
外部的資源：
- 主頁 [github.com]
相似套件：
Framework for Verilog RTL synthesis (documentation)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.
This package contains the manual.