[ 原始碼： verilator ]
套件：verilator（5.024-1 以及其他的）
fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
其他與 verilator 有關的套件
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- dep: libjs-sphinxdoc (>= 7.4)
- JavaScript support for Sphinx documentation
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- dep: perl
- Larry Wall's Practical Extraction and Report Language
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- dep: python3
- interactive high-level object-oriented language (default python3 version)
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- dep: sphinx-rtd-theme-common (>= 2.0.0+dfsg)
- sphinx theme from readthedocs.org (common files)
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- sug: gtkwave
- VCD (Value Change Dump) file waveform viewer