套件：gplcver（2.12a-3） [debports]
Verilog simulator
Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM.
其他與 gplcver 有關的套件
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- dep: libc6.1 (>= 2.35)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6.1-udeb