[ sid ]
[ experimental ]
套件：yosys-abc（0.33-6~exp3） [debports]
試製（Experimental）套件
警告：這個套件來自於 experimental 發行版。這表示它很有可能表現出不穩定或者出現 bug ，甚至是導致資料損失。請務必在使用之前查閱 changelog 以及其他潛在的文件。
Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.
其他與 yosys-abc 有關的套件
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- dep: libbz2-1.0
- high-quality block-sorting file compressor library - runtime
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- dep: libc6 (>= 2.38)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6-udeb
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- dep: libgcc-s2 (>= 4.2.1)
- GCC 支援函式庫
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- dep: libreadline8t64 (>= 6.0)
- GNU readline 與 history 函式庫，執行時期函式庫
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- dep: libstdc++6 (>= 13.1)
- GNU Standard C++ Library v3
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- dep: zlib1g (>= 1:1.2.3.3)
- 壓縮函式庫 - 跑程式時用(runtime)