[ buster ]
[ 原始碼： alliance ]
套件：alliance（5.1.1-3）
VLSI CAD Tools
Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools.
A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator and a data-path compiler.
Alliance is the result of more than ten years effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).
Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.
Alliance provides CAD tools covering most of all the digital design flow:
* VHDL Compilation and Simulation * Model checking and formal proof * RTL and Logic synthesis * Data-Path compilation * Macro-cells generation * Place and route * Layout edition * Netlist extraction and verification * Design rules checking
其他與 alliance 有關的套件
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- dep: libc6 (>= 2.11)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6-udeb
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- dep: libgcc1 (>= 1:3.5)
- GCC 支援函式庫
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- dep: libice6 (>= 1:1.0.0)
- X11 Inter-Client Exchange library
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- dep: libsm6
- X11 Session Management library
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- dep: libstdc++6 (>= 5.2)
- GNU Standard C++ Library v3
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- dep: libx11-6
- X11 client-side library
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- dep: libxm4 (>= 2.3.4)
- Motif - X/Motif shared library
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- dep: libxpm4
- X11 pixmap library
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- dep: libxt6
- X11 toolkit intrinsics library