[ 原始碼： arachne-pnr ]
套件：arachne-pnr（0.1+20180909git840bdfd-1）
arachne-pnr 的相關連結
Debian 的資源：
下載原始碼套件 arachne-pnr：
- [arachne-pnr_0.1+20180909git840bdfd-1.dsc]
- [arachne-pnr_0.1+20180909git840bdfd.orig.tar.xz]
- [arachne-pnr_0.1+20180909git840bdfd-1.debian.tar.xz]
維護小組：
外部的資源：
- 主頁 [github.com]
相似套件：
Place and route tool for iCE40 family FPGAs
Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device.
Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development.
其他與 arachne-pnr 有關的套件
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- dep: arachne-pnr-chipdb
- Chip db files for arachne-pnr
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- dep: fpga-icestorm
- Tools to handle the bitstream format of Lattice iCE40 FPGAs
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- dep: libc6 (>= 2.17)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6-udeb
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- dep: libgcc1 (>= 1:3.0)
- GCC 支援函式庫
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- dep: libstdc++6 (>= 5.2)
- GNU Standard C++ Library v3
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- dep: yosys
- Framework for Verilog RTL synthesis