套件：iverilog（11.0-1）

[ 原始碼： iverilog  ]

Icarus verilog compiler

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

標籤: 領域: 電子學, 實做語言: C++, 使用者介面: interface::commandline, role::program

其他與 iverilog 有關的套件

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• dep: libc6 (>= 2.29)

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• dep: libgcc-s1 (>= 3.0)

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• dep: libreadline8 (>= 6.0)

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• dep: libstdc++6 (>= 5.2)

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• dep: zlib1g (>= 1:1.2.0)

  壓縮函式庫 - 跑程式時用(runtime)

• sug: gtkwave

  VCD (Value Change Dump) file waveform viewer

下載 iverilog

下載可用於所有硬體架構的

硬體架構	套件大小	安裝後大小	檔案
amd64	1，962。2 kB	6，872。0 kB	[檔案列表]