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[ 源代码: opensta  ]

软件包:opensta-dev(0~20191111gitc018cb2+dfsg-1.1)

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Gate-level Static Timing Analyzer - development files

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

This package contains the header files and some libraries for development.

标签: 软件开发: 函数库, 角色: 开发用函数库

下载 opensta-dev

下载可用于所有硬件架构的
硬件架构 软件包大小 安装后大小 文件
amd64 1,243.5 kB9,996.0 kB [文件列表]
arm64 16,353.5 kB118,124.0 kB [文件列表]
armel 1,118.8 kB8,101.0 kB [文件列表]
armhf 1,135.8 kB7,344.0 kB [文件列表]
i386 1,330.4 kB8,562.0 kB [文件列表]
mips64el 1,375.8 kB12,516.0 kB [文件列表]
ppc64el 1,328.1 kB11,320.0 kB [文件列表]
riscv64 4,074.0 kB43,896.0 kB [文件列表]
s390x 1,159.6 kB9,743.0 kB [文件列表]