源码包：covered（0.7.10-3）
本源码包构建了以下这些二进制包：
- covered
- Verilog code coverage analysis tool
- covered-doc
- Verilog code coverage analysis tool - documentation
其他与 covered 有关的软件包
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- adep: debhelper (>= 9)
- 用于 debian/rules 的帮助程序
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- adep: autotools-dev
- Update infrastructure for config.{guess,sub} files
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- adep: flex
- fast lexical analyzer generator
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- adep: bison
- YACC-compatible parser generator
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- adep: gperf
- Perfect hash function generator
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- adep: tcl-dev
- Tool Command Language (default version) - development files
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- adep: tk-dev
- Toolkit for Tcl and X11 (default version) - development files
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- adep: libxft2-dev
- 本虚包由这些包填实： libxft-dev
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- adep: gplcver (>= 2.12a-1.1)
- Verilog simulator
Download covered
| 文件 | 大小（单位：kB） | MD5 校验码 |
|---|---|---|
| covered_0.7.10-3.dsc | 1.7 kB | cf4eadabbb48f5f5b8fdfd34e8d67870 |
| covered_0.7.10.orig.tar.gz | 3,035.4 kB | 7f79e93471546810b166e9104236bda2 |
| covered_0.7.10-3.debian.tar.xz | 4.8 kB | bcdaa3169fe8844d2dbd2725bc442c39 |
- Debian 软件包源码仓库（VCS：Git）
- git://anonscm.debian.org/pkg-electronics/covered.git
- Debian 软件包源码仓库（可在线浏览）
- http://anonscm.debian.org/gitweb/?p=pkg-electronics/covered.git