软件包：covered（0.7.10-5）

[ 源代码： covered  ]

Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

标签: 领域: 电子学, 实做语言: C, 用户接口: interface::commandline, interface::graphical, X 窗口系统, 角色: 程序, 界面工具箱: uitoolkit::tk, use::viewing, X 窗口系统: 应用程序

其他与 covered 有关的软件包

• dep: libc6 (>= 2.34)

  GNU C 语言运行库：共享库
  同时作为一个虚包由这些包填实： libc6-udeb

• dep: libtcl8.6 (>= 8.6.0)

  Tcl (the Tool Command Language) v8.6 - run-time library files

• dep: libtk8.6 (>= 8.6.0)

  用于 Tcl 和 X11 的 Tk 工具箱 8.6 版 - 运行时文件

• dep: tklib

  standard Tk Library

• dep: zlib1g (>= 1:1.1.4)

  压缩库 - 运行时

• rec: iverilog

  Icarus verilog compiler

  或者 verilog

  本虚包由这些包填实： iverilog

  或者 gplcver (>= 2.12a-1.1)

  Verilog simulator

下载 covered

下载可用于所有硬件架构的

硬件架构	软件包大小	安装后大小	文件
ppc64el	512.5 kB	2,949.0 kB	[文件列表]