软件包：yosys-dev（0.33-6~exp2） [debports]
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警告：这个软件包来自于 experimental 发行版。这表示它很有可能表现出不稳定或者出现 bug ，甚至是导致资料损失。请务必在使用之前查阅 changelog 以及其他潜在的文档。
Framework for Verilog RTL synthesis (development files)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.
This package contains the headers and programs needed to build yosys plugins.
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