Пакет: qflow (1.3.17+dfsg.1-3 и другие) [debports]

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Open-Source Digital Synthesis Flow

This is a complete tool chain for synthesizing digital circuits starting from verilog source and ending in physical layout for a specific target fabrication process. In the world of commercial electronics, digital synthesis with a target application of a chip design is usually bundled into large EDA software systems. As commercial electronics designers need to maintain cutting-edge performance, these commercial toolchains get more and more expensive, and have largely priced themselves out of all but the established integrated circuit manufacturers. This leaves an unfortunate gap where startup companies and small businesses cannot afford to do any sort of integrated circuit design.

Qflow tries to fill this gap.

Другие пакеты, относящиеся к qflow

• dep: berkeley-abc

  ABC - A System for Sequential Synthesis and Verification

• dep: graywolf

  Placement for digital VLSI design

• dep: libc6 (>= 2.34)

  библиотека GNU C: динамически подключаемые библиотеки
  также виртуальный пакет, предоставляемый libc6-udeb

• dep: magic

  VLSI layout tool

• dep: netgen-lvs

  Netlist comparison - Layout vs Schematic (LVS)

• dep: opensta

  Gate-level Static Timing Analyzer

• dep: python3

  interactive high-level object-oriented language (default python3 version)

• dep: qrouter

  Multi-level, over-the-cell maze router

• dep: tcl

  Tool Command Language (default version) - shell

• dep: tcsh

  TENEX C Shell, an enhanced version of Berkeley csh

• dep: yosys

  Framework for Verilog RTL synthesis

• rec: python3-tk

  Tkinter - Writing Tk applications with Python 3.x

• rec: qflow-tech-osu018 (= 1.3.17+dfsg.1-3)

  Пакет недоступен

• rec: qflow-tech-osu035 (= 1.3.17+dfsg.1-3)

  Пакет недоступен

• rec: qflow-tech-osu050 (= 1.3.17+dfsg.1-3)

  Пакет недоступен

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Архитектура	Версия	Размер пакета	В установленном виде	Файлы
riscv64 (неофициальный перенос)	1.3.17+dfsg.1-3+b1	165,2 Кб	900,0 Кб	[список файлов]