Pacote: yosys (0.8-1)

[ Fonte: yosys  ]

Framework for Verilog RTL synthesis

This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.

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Download de yosys

Baixe para todas as arquiteturas disponíveis

Arquitetura	Tamanho do pacote	Tamanho instalado	Arquivos
amd64	1,839.7 kB	6,864.0 kB	[lista de arquivos]
arm64	1,618.5 kB	6,592.0 kB	[lista de arquivos]
armhf	1,568.0 kB	4,815.0 kB	[lista de arquivos]
i386	1,921.8 kB	7,259.0 kB	[lista de arquivos]